The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to solder bump structures in the packaging of semiconductor devices.
Faster, reliable, and higher-density circuits at lower costs are the goals for integrated circuit (IC) packaging. Conventional wirebond technology, the most common method for electrically connecting aluminum bonding pads on a chip surface to the package inner lead terminals on the lead-frame or substrate has proven to be low cost and reliable. But for the future, packaging goals will be met by increasing the density of chips and reducing the number of internal interconnections. Packages with fewer interconnecting links lower potential failure points, reduce the circuit resistance, and reduce interconnect capacitance, which affects electrical performance. The need to reduce the IC package to fit end-user applications (e.g., smart cards, palmtop computers, camcorders, and so on) is driving the new packaging designs that reduce size and overall profile. This reduction is offset by the need for handling larger amounts of parallel data lines, therefore driving the need to increase package input/output requirements with more leads.
Advanced packaging designs are regularly introduced to solve packaging challenges. One such advanced package design is flip chip. Flip chip is a packaging method of mounting the active side of a chip (with the surface bonding pads) toward the substrate (i.e., upside down placement of the bumped die relative to the wirebonding approach—thus the reason for the term “flip” chip). It provides the shortest path from the chip devices to the substrate and low cost interconnection for high volume automated production. There is also a reduction in weight and profile since leadframes or plastic packages are often not used. Flip chip technology uses solder bumps—usually formed from tin/lead solder in a 5% Sn and 95% Pb ratio—to interconnect the chip bonding pads to the substrate.
There are several methods known to those skilled in the art for producing solder bumps on a semiconductor device. FIGS. 1A–1E illustrate a prior art method of forming a bump on a substrate such as a semiconductor wafer. As shown in FIG. 1A, a semiconductor wafer 10 is provided having a base silicon substrate 12 with metal interconnect layers (not shown) overlying substrate 12 and an upper passivation layer 14, which may be one or more layers, that extends partially over a bond pad or contact pad 15 located on the upper surface of the semiconductor wafer 10. Passivation layer 14 has an opening overlying contact pad 15 so that electrical contact to an external circuit may be made from the semiconductor wafer 10. Contact pad 15 may be made from any of a variety of metals, such as aluminum, aluminum alloys, copper, and copper alloys. Typically, an under bump metallurgy (UBM) 16 is provided over the entire upper surface of semiconductor wafer 10 and over the upper surface of contact pad 15. UBM 16 may be composed of a plurality of individual layers of a variety of different metals and may be deposited by any of a variety of methods including electroless plating, sputtering, or electroplating. As shown in FIG. 1B, thereafter, a photoresist layer 22 is thereafter deposited over UBM 16 and patterned to provide an opening 24 overlying contact pad 15 on semiconductor wafer 10. Thereafter, a seed layer 26 may be deposited by conventional methods such as electroplating over UBM 16. An electrically conductive material 30 may then be deposited on top of seed layer 26 as shown in FIG. 1C and the electrically conductive material 30 includes solder, for example in a 63 weight percent Sn, 37 weight percent Pb eutectic composition. As shown in FIG. 1D, photoresist 22 is removed by plasma etching. FIG. 1E illustrates the step of reflowing the solder to provide a bump or ball 32 on semiconductor wafer 10.
After the solder bumps on a semiconductor device have been formed, typically an epoxy underfill is used in flip chip packaging. The underfill is typically an adhesive, such as an epoxy resin, that serves to reinforce the physical and mechanical properties of the solder joints between the IC chip and the substrate. The underfill improves the fatigue life of the packaged system, and also serves to protect the chip and interconnections from corrosion by sealing the electrical interconnections of the IC chip from moisture.
While the use of underfills has presented a solution to the problems associated with flip chip packaging, it has created new challenges for the semiconductor manufacturing process. In traditional solder bump structures, the new manufacturing steps required to apply the underfill, and to bake the assembly to harden the underfill, substantially complicate and lengthen the manufacturing process. An additional disadvantage to traditional solder bump structures in flip chip packaging has been that the use of an adhesive underfill can make it difficult, if not impossible, to disassemble the chip components when a defect is discovered after assembly of an electrical component. Because the solder assembly and underfill steps may occur simultaneously during the heating process, it is difficult to test the electronic assembly until the assembly is complete. Thus, if a defect is discovered, the underfill has already hardened, making removal and disassembly impractical. This results in increased production costs due to the waste of otherwise usable components.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved solder bump structure in advanced IC packaging such as flip chip that avoids the cost and reduced throughput concerns associated with conventional solder bump structures.